Stuck at Fault Testing Using Reversible Sequential Circuits

we propose the design of two vectors testable sequential circuits based on conservative logic gates. Any sequential circuit based on conservative logic gates can be tested for classical unidirectional stuck-at faults using only two test vectors. The two test vectors are all 1s, and all 0s. The designs of two vectors testable latches, masterslave flip-flops and double edge triggered (DET) flip-flops are presented. The importance of the proposed work lies in the fact that it provides the design of reversible sequential circuits completely testable for any stuck-at fault by only two test vectors, thereby eliminating the need for any type of scan-path access to internal memory cells. Intex Terms: Conservative logic, Fredkin gate, Flip-flops, Reversible logic.